Directory of C:\Users\bbeckman\tla\tla
03/14/2019 10:00 AM <DIR> .03/14/2019 10:00 AM <DIR> ..03/14/2019 08:35 AM <DIR> com03/14/2019 08:35 AM <DIR> examples03/14/2019 08:35 AM <DIR> javax03/14/2019 08:35 AM 4,959 License.txt03/14/2019 08:35 AM <DIR> META-INF03/14/2019 08:35 AM <DIR> model03/14/2019 08:35 AM <DIR> pcal03/14/2019 08:35 AM 645 README03/14/2019 10:24 AM <DIR> states03/14/2019 08:35 AM <DIR> tla2sany03/14/2019 08:35 AM <DIR> tla2tex03/14/2019 08:35 AM <DIR> tlc203/14/2019 08:35 AM <DIR> util 2 File(s) 5,604 bytes
C:\Users\bbeckman\tla\tla>set...CLASSPATH=c:\Users\bbeckman\tla\tla
...
C:\Users\bbeckman\tla\tla>java -versionjava version "1.8.0_201"Java(TM) SE Runtime Environment (build 1.8.0_201-b09)Java HotSpot(TM) 64-Bit Server VM (build 25.201-b09, mixed mode)
C:\Users\bbeckman\tla\tla>java tlc2.TLC ..\..\Documents\GitHub\TLASpecs\wireTLC2 Version 2.13 of 18 July 2018Running breadth-first search Model-Checking with seed 463029695021380323 with 1 worker on 12 cores with 14500MB heap and 64MB offheap memory (Windows 10 10.0 amd64, Oracle Corporation 1.8.0_201 x86_64).Parsing file C:\Users\bbeckman\Documents\GitHub\TLASpecs\wire.tlaParsing file C:\Users\bbeckman\tla\tla\tla2sany\StandardModules\Integers.tlaParsing file C:\Users\bbeckman\tla\tla\tla2sany\StandardModules\Naturals.tlaSemantic processing of module NaturalsSemantic processing of module IntegersSemantic processing of module wireStarting... (2019-03-14 10:31:01)Error: TLC threw an unexpected exception.This was probably caused by an error in the spec or model.See the User Output or TLC Console for clues to what happened.The exception was a java.lang.NullPointerExceptionjava.lang.NullPointerException at tlc2.tool.Spec.processSpec(Spec.java:204) at tlc2.tool.Tool.init(Tool.java:110) at tlc2.tool.AbstractChecker.<init>(AbstractChecker.java:91) at tlc2.tool.ModelChecker.<init>(ModelChecker.java:83) at tlc2.TLC.process(TLC.java:894) at tlc2.TLC.main(TLC.java:220)
Finished in 00s at (2019-03-14 10:31:01)
C:\Users\bbeckman\Documents\GitHub\TLASpecs>java ..\..\..\tla\tla\tlc2.TLC .\wireError: Could not find or load main class ..\..\..\tla\tla\tlc2.TLC
-------------------------------- MODULE wire --------------------------------EXTENDS Integers(*--algorithm wirevariables people = {"alice", "bob"}, acc = [p \in people |-> 5];define NoOverdrafts == \A p \in people: acc[p] >= 0end define; process Wire \in 1..2 variables sender = "alice", receiver = "bob", amount \in 1..acc[sender];begin CheckAndWithdraw: if amount <= acc[sender] then acc[sender] := acc[sender] - amount; Deposit: acc[receiver] := acc[receiver] + amount; end if;end process;end algorithm;*)\* BEGIN TRANSLATIONVARIABLES people, acc, pc
(* define statement *)NoOverdrafts == \A p \in people: acc[p] >= 0
VARIABLES sender, receiver, amount
vars == << people, acc, pc, sender, receiver, amount >>
ProcSet == (1..2)
Init == (* Global variables *) /\ people = {"alice", "bob"} /\ acc = [p \in people |-> 5] (* Process Wire *) /\ sender = [self \in 1..2 |-> "alice"] /\ receiver = [self \in 1..2 |-> "bob"] /\ amount \in [1..2 -> 1..acc[sender[CHOOSE self \in 1..2 : TRUE]]] /\ pc = [self \in ProcSet |-> "CheckAndWithdraw"]
CheckAndWithdraw(self) == /\ pc[self] = "CheckAndWithdraw" /\ IF amount[self] <= acc[sender[self]] THEN /\ acc' = [acc EXCEPT ![sender[self]] = acc[sender[self]] - amount[self]] /\ pc' = [pc EXCEPT ![self] = "Deposit"] ELSE /\ pc' = [pc EXCEPT ![self] = "Done"] /\ acc' = acc /\ UNCHANGED << people, sender, receiver, amount >>
Deposit(self) == /\ pc[self] = "Deposit" /\ acc' = [acc EXCEPT ![receiver[self]] = acc[receiver[self]] + amount[self]] /\ pc' = [pc EXCEPT ![self] = "Done"] /\ UNCHANGED << people, sender, receiver, amount >>
Wire(self) == CheckAndWithdraw(self) \/ Deposit(self)
Next == (\E self \in 1..2: Wire(self)) \/ (* Disjunct to prevent deadlock on termination *) ((\A self \in ProcSet: pc[self] = "Done") /\ UNCHANGED vars)
Spec == Init /\ [][Next]_vars
Termination == <>(\A self \in ProcSet: pc[self] = "Done")
\* END TRANSLATION
=============================================================================\* Modification History\* Last modified Mon Oct 15 18:38:35 PDT 2018 by rebcabin\* Created Mon Oct 15 13:09:48 PDT 2018 by rebcabin