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*From*: Felipe Oliveira Carvalho <felipekde@xxxxxxxxx>*Date*: Sat, 22 Apr 2023 10:27:30 -0300*References*: <975af696-81da-404b-ba99-0ab6d351ac08n@googlegroups.com>

Can instruction trace be modeled as a state transition system?

An idle thought, and may not be possible, but I was wondering if one could in theory verify an instruction trace decoder with TLA+?

If you have an input program to the test chip (let's call that Y), and then you generate a trace, and decode it, you'll get an output allegedly showing all the instructions actually executed (let's call that X).

How do you know that the instructions were correctly decoded? Is there some way in TLA+ to model Y, and then check that X is a valid implementation?

I guess one would have to assume that any discrepancy was introduced due to inaccurate decoding, not an issue with the chip though... --

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