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*From*: Stephan Merz <stephan.merz@xxxxxxxxx>*Date*: Wed, 30 Nov 2022 11:04:44 +0100*References*: <904caba2-762e-49a2-bea5-1dc6a3506929n@googlegroups.com> <498A9107-441B-4AA3-A9B1-F23E27AFAD86@gmail.com> <a244225f-f9a0-4db7-894c-cf52fd0bd762n@googlegroups.com>

Hi, you discovered why verification is not a panacea. You may prove the most elaborate theorems, but they are meaningless if your specification does not represent the actual system, and an inconsistent set of assumptions is just the most extreme example. Therefore, you need to be suspicious of success and validate your spec as much as you can. Simulation, as well as model checking non-properties and examining the counter-examples are useful for that. Note that this problem applies to both model checking and theorem proving. You should get suspicious if model checking completes very quickly, finds fewer reachable states than you expect, and/or if some actions are taken only rarely or never (TLC provides statistics for this). In theorem proving, get suspicious if a proof obligation that looks complicated is solved quickly and automatically, as it may indicate a contradiction between assumptions – although this is of course not always the case. Regards, Stephan
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**Follow-Ups**:**Re: [tlaplus] Simple contradiction proof***From:*jack malkovick

**References**:**[tlaplus] Simple contradiction proof***From:*jack malkovick

**Re: [tlaplus] Simple contradiction proof***From:*Stephan Merz

**Re: [tlaplus] Simple contradiction proof***From:*jack malkovick

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